This disclosure relates generally to enhanced thermal and structural performance within integrated circuit (IC) packaging structures. More particularly, the present disclosure is directed to the cooling of integrated circuit chips using a heat sink providing heat sink to module strain relief and thermal performance enhancement.
As heat is generated during the functioning of integrated circuit chips (ICs), the thermal resistance to the heat sink (Rint) must be small so that the operating temperature of the chip is low enough to assure the continued reliable operation of the device. The problem of heat removal becomes more difficult as chip geometries are scaled down and operating speeds are increased, resulting in increased power density. The ability to adequately cool the chips is therefore a limiting factor in the further increase of system performance. Integrated circuit chips mounted on substrates, and particularly in an array on a substrate such as is found in a single-chip module (SCM), dual-chip module (DCM) or a multi-chip module (MCM), present special cooling difficulties. In an MCM, the chips may be mounted very close together and nearly cover the whole top surface of the MCM. With such an arrangement, it may not be possible to use a heat spreader bonded directly to the back surface of the chips, as is sometimes used for isolated chips, to reduce the heat flux (power/unit area, i.e. W/cm2).
A common technique for removing heat from high-power IC's makes use of a cooling plate or heat sink which is thermally attached to the chips using a compliant thermally conductive material. Heat is removed from the cooling plate or heat sink by methods such as forced air cooling or circulating liquid coolants.
The ever increasing power densities associated with today's processing chips are pushing the “coolability” limits of existing thermal technologies to limit Rint. In DCM and MCM applications, the module typically is comprised of a one or more electronic chips or components. Balancing the most cost-effective substrate size and CP power density, the designer typically is faced with trade-offs and limitations associated with providing the best electrical & thermal performance possible. In addition, recent developments reveal that substrate sizing is more dependent on bottom-surface input/output (I/O) requirements than top-side component placement restrictions, thereby lending the design to additional approaches to improve Rint thermal performance. Typical thermal solution options include flat plate cooling (FPC) and direct-lid-attached/advanced-thermal-interfaces (DLA/ATI). For FPC (both traditional and small-gap-technology versions), two “separable” thermal interfaces are needed to complete the assembly (e.g., one each between the chip and cap, and between the cap and heat sink, respectively). In the case of DLA/ATI, only one “separable” thermal interface is used (heat spreader and heat sink). If a separable thermal interface can be eliminated and the heat spreader size can be made large enough, thermal performance can be enhanced. In the past, FPC and DLA/ATI solutions have been used in combination, but extension of its usefulness has been limited by the modules cap internal dimensions for encapsulating the substrate, thus limiting maximization of the spreader size. In addition to these constraints, high-end DCMs and MCMs typically require high bottom-surface metallurgy (BSM) I/O count and features that allow field replacement. These requirements drive the application of a force-actuated land-grid-array (LGA) interconnect methodology for the assembly of the module to the card assembly. Additionally, the LGA interconnection mechanism is usually targeted for leading edge, high performance modules that generate significant amounts of heat. Thus, thermal performance is important in the LGA interconnection mechanism design.
Accordingly, it is desired to address the effects of the electrical, thermal and mechanical requirements with an apparatus and method that resolves the coupled dimensional constraints so that an optimized system can be produced.